parasitic capacitance tests

Carlos Delfino Всі повідомлення цього користувача #38357 Hello everyone. A colleague told me that it is possible to perform certain transistor tests with a VNA, but he doesn't know where he saw such a practice. Is it really possible to perform such parasitic capacitance tests, and how would it be done? Could you point me to a tutorial on the subject? Thank you. -- Carlos Delfino Equipe Basicão da Eletrônica <https://basicaodaeletronica.com.br> Celular: (85) 985-205-490 (OI) - Aquiraz/CE <https://basicaodaeletronica.com.br>
Michael Robinson Всі повідомлення цього користувача #38370 First, in order to determine "parasitic capacitance" (which is generally determined by the sum total of the circuit components and their interaction within the circuit) you must determine the junction (P-N) capacitance of Base-Emitter and Base-Collector and "possibly" also Emitter-Collector capacitance, although the latter will be difficult to determine. I would try using a capacitor function of a meter to test each junction, since that meter function utilizes a voltage and frequency to determine a value within a given margin of error based on the tolerance of the instrument and also of the device under test (in the case of a true cap). A book on transistor circuits written by Malvino (whose first name escapes me after 50 years outside of the teaching environment) has several subtopics on P-N junction capacitance and associated lead length of the device (i.e., LC effect) that you might find of interest. There are likely several editions that followed the edition that I used. Best Regards, On Tue, Oct 15, 2024 at 10:57 AM Carlos Delfino via groups.io <consultoria= carlosdelfino.eti.br@groups.io> wrote: Hello everyone. A colleague told me that it is possible to perform certain transistor tests with a VNA, but he doesn't know where he saw such a practice. Is it really possible to perform such parasitic capacitance tests, and how would it be done? Could you point me to a tutorial on the subject? Thank you. -- Carlos Delfino Equipe Basicão da Eletrônica <https://basicaodaeletronica.com.br> Celular: (85) 985-205-490 (OI) - Aquiraz/CE <https://basicaodaeletronica.com.br> -- Michael L Robinson, KC0TA FREEDOM is NEVER given; It Is WON! “In the beginning of a change the Patriot is a scarce man, and brave, and hated and scorned. When his cause succeeds, the timid join him, for then it costs nothing to be a Patriot.” ― Mark Twain When Tyranny becomes Law, Revolution becomes Duty!
Carlos Delfino Всі повідомлення цього користувача #38371 Hello Michael, thank you for your attention. In this case, the question is particularly about using the VNA, using an LCR or a common capacitance meter I have no doubts. -- Carlos Delfino Equipe Basicão da Eletrônica <https://basicaodaeletronica.com.br> Celular: (85) 985-205-490 (OI) - Aquiraz/CE <https://basicaodaeletronica.com.br> Em ter., 15 de out. de 2024 às 16:06, Michael Robinson via groups.io < kc0ta.us@...> escreveu: переключити цитоване повідомлення Показати цитований текст First, in order to determine "parasitic capacitance" (which is generally determined by the sum total of the circuit components and their interaction within the circuit) you must determine the junction (P-N) capacitance of Base-Emitter and Base-Collector and "possibly" also Emitter-Collector capacitance, although the latter will be difficult to determine. I would try using a capacitor function of a meter to test each junction, since that meter function utilizes a voltage and frequency to determine a value within a given margin of error based on the tolerance of the instrument and also of the device under test (in the case of a true cap). A book on transistor circuits written by Malvino (whose first name escapes me after 50 years outside of the teaching environment) has several subtopics on P-N junction capacitance and associated lead length of the device (i.e., LC effect) that you might find of interest. There are likely several editions that followed the edition that I used. Best Regards, On Tue, Oct 15, 2024 at 10:57 AM Carlos Delfino via groups.io <consultoria= carlosdelfino.eti.br@groups.io> wrote: Hello everyone. A colleague told me that it is possible to perform certain transistor tests with a VNA, but he doesn't know where he saw such a practice. Is it really possible to perform such parasitic capacitance tests, and how would it be done? Could you point me to a tutorial on the subject? Thank you. -- Carlos Delfino Equipe Basicão da Eletrônica <https://basicaodaeletronica.com.br> Celular: (85) 985-205-490 (OI) - Aquiraz/CE <https://basicaodaeletronica.com.br> -- Michael L Robinson, KC0TA FREEDOM is NEVER given; It Is WON! “In the beginning of a change the Patriot is a scarce man, and brave, and hated and scorned. When his cause succeeds, the timid join him, for then it costs nothing to be a Patriot.” ― Mark Twain When Tyranny becomes Law, Revolution becomes Duty!
W0LEV Всі повідомлення цього користувача #38373 If a transistor were biased as in use, one could decouple the DC bias from the VNA and measure the junction capacitances. Just keep the RF drive extremely low as to not upset the bias point of the DUT. This does not seem like rocket science. As a test article, remember the EB junction of many BFTs can serve as a varactor. Dave - WØLEV On Tue, Oct 15, 2024 at 7:15 PM Carlos Delfino via groups.io <consultoria= carlosdelfino.eti.br@groups.io> wrote: Hello Michael, thank you for your attention. In this case, the question is particularly about using the VNA, using an LCR or a common capacitance meter I have no doubts. -- Carlos Delfino Equipe Basicão da Eletrônica <https://basicaodaeletronica.com.br> Celular: (85) 985-205-490 (OI) - Aquiraz/CE <https://basicaodaeletronica.com.br> Em ter., 15 de out. de 2024 às 16:06, Michael Robinson via groups.io < kc0ta.us@...> escreveu: First, in order to determine "parasitic capacitance" (which is generally determined by the sum total of the circuit components and their interaction within the circuit) you must determine the junction (P-N) capacitance of Base-Emitter and Base-Collector and "possibly" also Emitter-Collector capacitance, although the latter will be difficult to determine. I would try using a capacitor function of a meter to test each junction, since that meter function utilizes a voltage and frequency to determine a value within a given margin of error based on the tolerance of the instrument and also of the device under test (in the case of a true cap). A book on transistor circuits written by Malvino (whose first name escapes me after 50 years outside of the teaching environment) has several subtopics on P-N junction capacitance and associated lead length of the device (i.e., LC effect) that you might find of interest. There are likely several editions that followed the edition that I used. Best Regards, On Tue, Oct 15, 2024 at 10:57 AM Carlos Delfino via groups.io <consultoria= carlosdelfino.eti.br@groups.io> wrote: Hello everyone. A colleague told me that it is possible to perform certain transistor tests with a VNA, but he doesn't know where he saw such a practice. Is it really possible to perform such parasitic capacitance tests, and how would it be done? Could you point me to a tutorial on the subject? Thank you. -- Carlos Delfino Equipe Basicão da Eletrônica <https://basicaodaeletronica.com.br> Celular: (85) 985-205-490 (OI) - Aquiraz/CE <https://basicaodaeletronica.com.br> -- Michael L Robinson, KC0TA FREEDOM is NEVER given; It Is WON! “In the beginning of a change the Patriot is a scarce man, and brave, and hated and scorned. When his cause succeeds, the timid join him, for then it costs nothing to be a Patriot.” ― Mark Twain When Tyranny becomes Law, Revolution becomes Duty! -- Dave - WØLEV -- Dave - WØLEV
Jim Lux Всі повідомлення цього користувача #38374 I would think that you would do it by setting up a circuit with the transistor in an operating configuration (whether CE, CC, or CB) with biases, and DC blocks to/from the VNA and then measuring the parameters, comparing with a model (e.g. SPICE). Surely there is a HP/Agilent/Keysight application note on measuring transistor parameters with a VNA - that's where I would start. The trick is that the apparent values are affected by the gain of the active device (assuming you're measuring it with biases applied). E.g. the Miller effect.
Carlos Delfino Всі повідомлення цього користувача #38376 Thank you, I will study what was suggested. -- Carlos Delfino Equipe Basicão da Eletrônica <https://basicaodaeletronica.com.br> Celular: (85) 985-205-490 (OI) - Aquiraz/CE <https://basicaodaeletronica.com.br> Em ter., 15 de out. de 2024 às 16:39, Jim Lux via groups.io <jimlux= earthlink.net@groups.io> escreveu: переключити цитоване повідомлення Показати цитований текст I would think that you would do it by setting up a circuit with the transistor in an operating configuration (whether CE, CC, or CB) with biases, and DC blocks to/from the VNA and then measuring the parameters, comparing with a model (e.g. SPICE). Surely there is a HP/Agilent/Keysight application note on measuring transistor parameters with a VNA - that's where I would start. The trick is that the apparent values are affected by the gain of the active device (assuming you're measuring it with biases applied). E.g. the Miller effect.
W0LEV Всі повідомлення цього користувача #38379 QUOTE (Jim Lux): The trick is that the apparent values are affected by the gain of the active device (assuming you're measuring it with biases applied). E.g. the Miller effect. ************************************************************************************************ Making the measurement with no bias gives little to no information. Note that all the datasheets of our modern MMICs, HF, and µwave transistors, be they BJTs or FETs, give the S-parameters at specific bias points. Measuring capacitance with no realistic bias makes no sense. Dave - WØLEV On Tue, Oct 15, 2024 at 7:56 PM Carlos Delfino via groups.io <consultoria= carlosdelfino.eti.br@groups.io> wrote: Thank you, I will study what was suggested. -- Carlos Delfino Equipe Basicão da Eletrônica <https://basicaodaeletronica.com.br> Celular: (85) 985-205-490 (OI) - Aquiraz/CE <https://basicaodaeletronica.com.br> Em ter., 15 de out. de 2024 às 16:39, Jim Lux via groups.io <jimlux= earthlink.net@groups.io> escreveu: I would think that you would do it by setting up a circuit with the transistor in an operating configuration (whether CE, CC, or CB) with biases, and DC blocks to/from the VNA and then measuring the parameters, comparing with a model (e.g. SPICE). Surely there is a HP/Agilent/Keysight application note on measuring transistor parameters with a VNA - that's where I would start. The trick is that the apparent values are affected by the gain of the active device (assuming you're measuring it with biases applied). E.g. the Miller effect. -- Dave - WØLEV -- Dave - WØLEV
Roger Need Всі повідомлення цього користувача #38384 Carlos, I suggest you always search the archives for old posts on a subject. Often you will find the topic has been discussed before (often at great length). Here is one that will interest you. ... https://groups.io/g/nanovna-users/topic/measure_input_capacitance_of/102376532 Roger
Carlos Delfino Всі повідомлення цього користувача #38385 Thanks Roger. -- Carlos Delfino Equipe Basicão da Eletrônica <https://basicaodaeletronica.com.br> Celular: (85) 985-205-490 (OI) - Aquiraz/CE <https://basicaodaeletronica.com.br> Em ter., 15 de out. de 2024 às 19:08, Roger Need via groups.io <sailtamarack@...> escreveu: переключити цитоване повідомлення Показати цитований текст Carlos, I suggest you always search the archives for old posts on a subject. Often you will find the topic has been discussed before (often at great length). Here is one that will interest you. ... https://groups.io/g/nanovna-users/topic/measure_input_capacitance_of/102376532 Roger

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