Looking for a way to extend thermal modeling to any power device since thermal models from Manufacturers are few and far between. Also to be used as a teaching aid for new users. Absolute accuracy is not an issue. 

 

I've gone through many of the thermal analysis I found on this forum and diyAudio using LTSpice and then replicated most using Qucs-S/ngspice. ngspice has a VDMOS thermal model and it works with most Manufacturer thermal models. I've done VDMOS, SiC Mosfet, IGBT, GaN.

 

Having problems finding BJT thermal models so I thought this Design Idea provided a possible method. I assume it's similar to the VDMOS thermal analysis done in LTspice and ngspice. I assume Rthjc and Cthj used in the VDMOS models will need to be estimated for the BJT devices as well.

 

I can replicate the Spice sub-circuits used in the EDN Design Idea but I don't know what formulas were used to extract temp rise. I added another screenshot of what I'm working on.

There are various aspects to thermal modelling. As you say, there are many MOSFETs provided with thermal models, from various manufacturers. If the device you're interested in is catered for, then plugging their thermal model into a test circuit is easy. I uploaded a simple example schematic that shows how to use them a while ago.

This is well and good if a thermal is provided, as in the majority of (power) MOSFETs. The one in my example is a six stage RC ladder, which are very accurate, and are optimised using modern thermal analysis techniques.

For BJTs, equivalent models are almost unknown. I think this is mostly because the devices were designed in the last century, even premium devices like the Onsemi MJL3281/MJL1302 ranges, which originally came from Toshiba in the 1990s. For the vast majority of power devices, the Rthjc is on the datasheet. Rohm helpfully provide a document listing Rthjc for various of their packages and mounting configurations. However, this is a static figure and doesn't include any thermal capacities, which constitute the capacitances.

Without an advanced thermal model, the best I usually aim for is a two or three stage RC model. The dominant stages in a thermal model are the die, lead frame and package/PCB in series. You can embellish the design if there is more than one significant heat path, for example if both top and bottom a the package are cooled.

You can estimate thermal resistances and capacitances from basic physics and a drawing of the packaged device. In addition, you need to know the physical properties of the various materials:

For example, to estimate the thermal resistance:

               H
Rth (K/W) = ⎯⎯⎯⎯          where: H = Thickness, θ = Thermal conductivity, A = Area
             θ * A

For example, if the die attach eutectic solder layer is 50μm thick and its thermal conductivity is 50W/m.K, then its Rth is 1K/W for a die 1mm square. (Take care with units!)

Similarly, you can estimate the thermal capacity of the die from:

Cth (J/K) = A * H * ρ * c     where: H = Thickness, A = Area, ρ = Density, c = Specific heat

Using the thermal-electrical unit equivalence, Rth => Relec (Ω) and Cth => Celec (F). For it to work correctly, Thermal power (W) => Electrical current (A).

The elements of the physical model can be built up in an CR shunt-series ladder from die to case to ambient. Terminate with a voltage source representing the ambient temperature.

In an effort to be helpful, I've constructed a thermal model of a power transistor mounted on a PCB using the PCB top and bottom planes as a modest heatsink. The schematic shows how to calculate the thermal resistances and capacities, but in some cases the actual numbers have been guessed or made up.

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Isn't the goal of such simulations to find out how the temperature variation modulates the operating point of the device, thus causing extra distortion? For this to work, the model of these devices (and the simulator itself) must support individual (per device) temperature ports.
Given that the EDN thermal simulation needs to run for at least 500s, THD calculation can become a bit time intensive...

Isn't the goal of such simulations to find out how the temperature variation modulates the operating point of the device, thus causing extra  distortion? For this to work, the model of these devices (and the simulator itself) must support individual (per device) temperature ports.
Given that the EDN thermal simulation needs to run for at least 500s, THD calculation can become a bit time intensive...

Whilst that could perfectly be the object of a simulation, it isn't the object of this one. The whole idea was to try and lift some of the mystery regarding thermal analysis, not tune the distortion performance of an unspecified circuit.

Perhaps you should read what the OP was asking about:

Having problems finding BJT thermal models so I thought this Design Idea provided a possible method. I assume it's similar to the VDMOS thermal analysis done in LTspice and ngspice. I assume Rthjc and Cthj used in the VDMOS models will need to be estimated for the BJT devices as well.

 

I can replicate the Spice sub-circuits used in the EDN Design Idea but I don't know what formulas were used to extract temp rise. I added another screenshot of what I'm working on.

As far as dynamic modulation of the device's parameters by temperature changes, that will have to wait for another day.

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Thermal simulations are usually done to assess the limits of the system, before it releases the magic smoke.

Tony;