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Double pulse test turn-on problem

 

Respected everyone, 

Here is my double pulse test result (https://groups.io/g/LTspice/album?id=298508). I'm trying to understand why the waveform oscillates specifically during the second turn-on event. Could these oscillations be due to parasitic inductances or capacitances, reverse recovery effects or gate drive issues? I would appreciate any insights or suggestions on what might be causing this behavior and how to mitigate it potentially.
For context, my measurement setup uses a DC bus voltage (Vdc) of 48V, with a switching current of approximately 20A. The load consists of a 1mH inductor with 400mΩ resistance. The device under test (DUT) is the low-side MOSFET in a half-bridge configuration.

Thank you for your assistance!
Krunal
 

On 24/10/2024 16:56, krunal patel wrote:
Here is my double pulse test result (https://groups.io/g/LTspice/album?id=298508). I'm trying to understand why the waveform oscillates specifically during the second turn-on event. Could these oscillations be due to parasitic inductances or capacitances, reverse recovery effects or gate drive issues? I would appreciate any insights or suggestions on what might be causing this behavior and how to mitigate it potentially.
For context, my measurement setup uses a DC bus voltage (Vdc) of 48V, with a switching current of approximately 20A. The load consists of a 1mH inductor with 400mΩ resistance. The device under test (DUT) is the low-side MOSFET in a half-bridge configuration.
How are we supposed to know why it is oscillating? You haven't showed us any schematic. Or is this an actual measurement? If so, perhaps you should look and the track length between the half-bridge driver and the gate.

--
Regards,
Tony
 

The short answer is yes. All or none of these may be causing your issues, What kind of device is it? Si, SiC, GaN, etc will all have challanges when measuring the device(s). Parasitics "usually" impact the frequency component of the oscillation, Reverse recovery and the DUT characteristics "usually" impact the Peak value of the oscillation and the rate of decay, while the gate drive issues could cause all of them independently.
 
Have you tried increasing the Rg value? Also, slowing down the response will give you some insight into what the actual cause(s) are. There is an awful lot to unpack from the initial measurement. I doubt many can tell you absolutely what is the cause (probably multiple causes), but be assured that all DPT results show oscillations. You'll have to run several tests to know how to apportion the causes and determine some possible improvements. Where you actually take and reference your measurements may also impact your results.
 
Just my thoughts... BTW, getting a simulation to match the measurements is a REAL challenge... 
 

On Thu, Oct 24, 2024 at 07:59 AM, krunal patel wrote:
Respected everyone, 

Here is my double pulse test result (https://groups.io/g/LTspice/album?id=298508). I'm trying to understand why the waveform oscillates specifically during the second turn-on event. Could these oscillations be due to parasitic inductances or capacitances, reverse recovery effects or gate drive issues? I would appreciate any insights or suggestions on what might be causing this behavior and how to mitigate it potentially.
For context, my measurement setup uses a DC bus voltage (Vdc) of 48V, with a switching current of approximately 20A. The load consists of a 1mH inductor with 400mΩ resistance. The device under test (DUT) is the low-side MOSFET in a half-bridge configuration.

Thank you for your assistance!
Krunal
 
Hi Krunal,
it would be helpful to see how your circuit looks like. Can you send your LTspice .asc-file ? To me the picture you've posted is an indication for freewheeling effects, right after turning off the switching elements. It seems there are no damping network or any soft switching measures involved in the circuit. But this is just a guess about a "non-visible" circuit.
----
regards
Udo       

 
 
 

Hi Krunal,
 
This is the difference between theory and practice
You have to consider many effects. Here are the major ones :
- Reverse recovery,
- Loop inductance,
- Package leakage inductances
- Gate distribution network
- Non-linear effects
- Output capacitors
 
On top, Probes effects (capacitance for voltage probe and inductance for current probe)
 
Best regards, Didier
 
 

Thank you for your response. To clarify, the double pulse test (DPT) was performed on actual hardware, and I’ve attached a photo (https://groups.io/g/LTspice/album?id=298508) of the complete test result and hardware for your reference.
For the measurements, I used differential probes to capture both the drain-to-source voltage and gate-to-source voltage. The gate resistor values used during the test were 47Ω for turn-on and 12Ω for turn-off, with a Schottky diode placed in series with the turn-off resistor.
 

On 25/10/2024 10:25, krunal patel wrote:
Thank you for your response. To clarify, the double pulse test (DPT) was performed on actual hardware, and I’ve attached a photo (https://groups.io/g/LTspice/album?id=298508) of the complete test result and hardware for your reference.
For the measurements, I used differential probes to capture both the drain-to-source voltage and gate-to-source voltage. The gate resistor values used during the test were 47Ω for turn-on and 12Ω for turn-off, with a Schottky diode placed in series with the turn-off resistor.
Just to further clarify, this is not a simulation? So, until now this has nothing to do with LTspice. It is a request for help in hardware debugging.

Did you try simulating your design? Perhaps that would help clarify why things are happening.

--
Regards,
Tony
 

As shown on your photo(s), you are using separate power supplies for your Gate drivers, from which the power supply for the Top Gate driver is floating. This could also produce oszillations, if parasitic capacitances are present between the supplies. Is there a reason, why you did not use a bootstrap arrangement to supply the Top Gate Driver ?
 
By the way, if you are afraid of double or multiple turn-on/turn-off pulse transitions within a switching period, a double-pulse suppression circuit would be the choice to prevent damages.
 
Regards,
Udo 

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