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simulating PI controller AC responce effect of ERROR signal of a PLL
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Hello My PLL is suffering from error signal DC drifting over time.
I have built a PI controller AC responce and pulse responce shown below.
The main this I want this controller to do is to keep the error sinal on the same DC level and make it stop drifitng.
In PLL we set the error signal to "travel" around 0V .
unlike regular amplifier when we have input and output , where I can see how CW signal will be amplified. In my case I dont know how the PI controller will handle the DC drift of my pll.
Is there a way to do something in LTSPICE?
Also I added some videos from the lab so you could understand the drift situation I got and in general the situation. Thanks.
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On Sun, Dec 15, 2024 at 02:19 PM, john23 wrote:
Where exactly is the error signal? Is it the input voltage to the VCO? Or the output voltage from the phase detector? Or elsewhere? Did you observe that it is drifting by building the PLL and measuring it, not simulating it? Do you know that the PLL is in-lock, or is it out-of-lock? That is a key thing you really need to know first.
Do not upload pictures of schematics! Upload the schematic itself.
OK, your schematic of the error amplifier seems to be simple enough so that it can be replicated and it might even work. But don't ever rely on the picture of a schematic, when the LTspice schematic itself exists, and it carries much more information than the picture does.
Where is the pulse response? I do not see the pulse response in any of the pictures you uploaded today.
One of the "features" of a PLL is that it is self-correcting, where it drives whatever voltage is needed in order to bring the PLL into lock. If it is in lock, then the control voltage might be a (somewhat) arbitrary voltage, depending on the characteristics of the VCO. It will not always be the same. I hope you understand, this is how PLLs work. Please explain, what and where exactly is the "DC drift of my pll"?
In this case, I think it is not likely that you can do something differently in LTspice than in the hardware. Unless, what you are asking for is a way to add drift to the simulation, to simulate components that have drift. That can be done. But I don't understand the question.
Andy
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Drift in the feedback voltage of a PLL usually means that the VCO has poor stability. For example, this WILL happen if the VCO frequency is controlled by a varactor diode (varactor diodes have a substantial capacitance temperature coefficient). That said, PLLs are NOT intended modulation detection that extends to DC. The phase detector and the loop filter are specifically designed NOT to go to DC.
If that is what you want, you are using the wrong tool!
Jim Wagner
Oregon Research Electronics
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To amplify this slightly, a PLL loop is DESIGNED to drive the frequency difference AND the phase difference between the two signals to zero. With that design goal, there cannot be a DC frequency difference. If you want to "demodulate" static frequency differences, then you will need a different circuit.
Jim Wagner
Oregon Research Electronics
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The signal that I desire in PLL is 0V , when my YIG is drifting in one direction that means that my error signa is like a ramp.
0 and then going up(thus making the frequency move in one direction). The output of the PI controller is an invertion to that ramp. The output of the controller needs to influence the drift of the at the input.
How can I simulate this effect of controller output influence the input?
LTspice file is attached.
https://groups.io/g/LTspice/files/z_groups.io/Files-sorted-by-message-number/msg_ZZZZZZ/john23%20%233/Draft2.asc |
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john23,
I'm going to tell this to you again:
DO NOT upload your files into various subdirectories within the group's Files section. Upload into the Temp directory only.
Read and heed. You have been a member of this group long enough to know this already.
Andy
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On Mon, Dec 16, 2024 at 01:27 PM, john23 wrote:
It does mean that the control voltage to the YIG VCO is a ramp. But the error voltage from the doubly balanced mixer (phase detector) might not be a ramp; it might be a steady voltage (after filtering to remove higher frequency components). If it was a ramp, then the VCO's input voltage would be parabolic, not linear.
Well, that depends on what you want to simulate and what you expect to see.
If you just want to see that the control voltage to the VCO changes like a ramp, then feed a small DC voltage into your loop filter (the LT1028 circuit in Draft2.asc). With that input, its output would be a ramp and you should see that by simulating it. That simulation would represent the condition where the phase error is constant, and the PLL is probably not in lock.
If you want to see how the components of the PLL cause that to happen, then I think you will need to find/create models for all the PLL's parts, add a source to force the VCO's transfer function to drift over time, and them simulate the whole PLL in action.
Full PLL simulations are likely to simulate slowly, because the simulation needs to track the RF waveform. I'm guessing your RF frequencies are rather high. That forces the simulator to use small timesteps, and it may take many many timesteps to accumulate enough time to see the dynamics of the feedback loop, and even longer to see VCO drift. You may want to re-consider whether you really want to do that, or need to do that.
FYI, in your simulation of "Draft2.asc", you should disable LTspice's waveform compression:
.options plotwinsize=0
because the waveform compression takes great advantage of the fact that all signals vary either linearly or quadratically, which the waveform compression can re-create easily using very few saved timepoints. You might not want it to do that.
I'll remind you once again that screenshots of schematics are not user-friendly or helpful. Neither is the screenshot of voltages that have no explanation. Why show us something that serves no purpose? If you had a purpose for showing those waveforms, please explain it.
Andy
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Hello Andy the purpose of shown screen shot is to see help you visualise my thought so I'll be more clear.
Also i will only post in the TEMP folder.
I want to see a simulate a system with P controller only VS PI controller.
Can you show an example of an input that P cant handle while PI is handling.
Some simple simulation i can see in LTspice? |
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On 12/17/24 3:13 PM, Andy I via groups.io wrote:
What is P controller?Usually this refers to: Proportional Integral Derivative With variations using one or more of the three. Although these days calling something a PI controller could refer to a Raspberry Pi so it is best to be clear. But it is really hard to test a controller without something to stand in for the system being controlled. -- http://davesrocketworks.com David Schultz |
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If you are interested in seeing the VCO drift across a range of frequencies, take your simulation and shove an FM tone into the PLL reference port and then observe the varactor voltage.
Make sure your FM tone contains expected VCO tone when varactor voltage == 0V at some central design tone. A PLL is a closed loop control system incorporating one of many ( possibly adaptable ) filters in the control signal path.
Opening the loop causes the PLL to die.
You can think of PLL filter as a PID controller however existing, histroical PLL filter discussion while comparable to PID analysis is framed slightly differently in terms of application.
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