Hello Group,

I discovered LTSpice a few days ago and I find it very usefull, fun
and easy-to-use :-)

I am now trying to use mixed-mode simulation, and I cannot edit nor
see the models of simple parts like DFLOP (I just want to modify Hold
Time, Threshold, etc.). I did it easily for simple analog parts (like
nmos,pmos), but no way to find a file (even after a search in the
help files and FAQ) for digital parts...maybe I should buy new
glasses.

A Hint?

Thank you in advance for your help

Christian Néel

--- In LTspice@..., "neel_christian <neel_c@c...>"
<neel_c@c...> wrote:

Hello Group,

I discovered LTSpice a few days ago and I find it very usefull,

fun

and easy-to-use :-)

I am now trying to use mixed-mode simulation, and I cannot edit nor
see the models of simple parts like DFLOP (I just want to modify

Hold

Time, Threshold, etc.). I did it easily for simple analog parts

(like

nmos,pmos), but no way to find a file (even after a search in the
help files and FAQ) for digital parts...maybe I should buy new
glasses.

A Hint?

Hello Christian,
new glasses wouldn't help. I had the same question half a year ago.
The developer of LTSpice, Mike Engelhardt, kindky send me the
necessary information.
By the way, he is around here in the group as Panama Mike,
but keep it for yourself. It is a secret.

The attached sample circuit helps to understand the syntax.
This file is also from Mike.

Hello Mike,
are there even more parameters for digital parts?

Best Regards
Helmut


Original answer from Mike:
--------------------------
The low and high levels are given with Vlow and Vhigh. The
logic thresholds default to half way between but can be
specified with ref. Hysteresis is not possible for gates,
but only for the Schmitt devices. Attached is and example
that hopefully illustrates. Tripdt is a type of temporal
accuracy it should strive for in switching.

Sample circuit file "gate.asc":
-------------------------------

Version 3
SHEET 1 892 692
WIRE 408 304 408 320
WIRE 420 292 436 292
WIRE 420 300 520 300
WIRE 344 356 344 340
WIRE 344 320 344 296
WIRE 344 296 404 296
WIRE 520 300 520 308
WIRE 520 328 520 340
WIRE 408 244 408 260
WIRE 420 232 436 232
WIRE 404 236 344 236
WIRE 344 236 344 296
WIRE 344 236 344 200
WIRE 344 200 404 200
WIRE 420 200 452 200
WIRE 404 204 404 212
FLAG 408 320 GND
FLAG 344 356 GND
FLAG 520 340 GND
FLAG 408 260 GND
FLAG 404 212 GND
SYMBOL digital&#92;and 412 280 R0
WINDOW 0 4 6 Left 0
WINDOW 3 4 28 Left 0
WINDOW 39 4 44 Left 0
WINDOW 40 4 52 Left 0
WINDOW 123 4 36 Left 0
SYMATTR InstName A1
SYMATTR Value Vhigh=5
SYMATTR Value2 Vlow=0 Rout=100
SYMATTR SpiceModel AND
SYMATTR SpiceLine Ref=2 Td=50n tripdt=3n
SYMATTR SpiceLine2 Trise=20n Tfall=40n
SYMBOL voltage 344 316 R0
WINDOW 0 6 4 Left 0
WINDOW 3 6 26 Left 0
SYMATTR InstName V1
SYMATTR Value pulse(0 5 0 100n 100n 0 200n)
SYMBOL res 516 304 R0
WINDOW 0 9 10 Left 0
WINDOW 3 9 19 Left 0
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL digital&#92;and 412 220 R0
WINDOW 0 4 6 Left 0
WINDOW 3 4 28 Left 0
WINDOW 39 4 44 Left 0
WINDOW 40 4 52 Left 0
WINDOW 123 4 36 Left 0
SYMATTR InstName A2
SYMATTR Value Vhigh=5
SYMATTR Value2 Vlow=0 Rout=100
SYMATTR SpiceModel AND
SYMATTR SpiceLine Ref=2 Td=50n tripdt=3n
SYMATTR SpiceLine2 Tau=10n
SYMBOL digital&#92;schmtbuf 404 184 R0
WINDOW 0 2 8 Left 0
WINDOW 3 5 24 Left 0
WINDOW 123 5 32 Left 0
SYMATTR InstName A3
SYMATTR Value Vt=2.5 Vh=1
SYMATTR Value2 tripdt=3n
SYMATTR SpiceModel SCHMITT
text 328 368 Left 0 !.tran 1u

--- In LTspice@..., "Helmut Sennewald >

The attached sample circuit helps to understand the syntax.
This file is also from Mike.

Hello Mike,
are there even more parameters for digital parts?

Best Regards
Helmut

Thank you very much Helmut,

In the meantime, I debugged my digital design (a simple FSM) on
another mixed-mode simulator (evaluation version of Microcap). Now
I'll try to implement it with LTSpice where my main analog design is,
using Mikes's example.
Probably more feedback at the end of the week-end.

Best regards

Christian

--- In LTspice@..., "neel_christian <neel_c@c...>"
<neel_c@c...> wrote:

--- In LTspice@..., "Helmut Sennewald >

The attached sample circuit helps to understand the syntax.
This file is also from Mike.

Hello Mike,
are there even more parameters for digital parts?

Best Regards
Helmut

Thank you very much Helmut,

In the meantime, I debugged my digital design (a simple FSM) on
another mixed-mode simulator (evaluation version of Microcap). Now
I'll try to implement it with LTSpice where my main analog design

is,

using Mikes's example.
Probably more feedback at the end of the week-end.

Hello Christian,
I forgot a very important detail.
You have to specify some delay Td for every flipflop.

All my simulated counters and flipflops have run as expected only
when I specified a delay for every flipflop(e.g. Td=10ns).

Your FSM(Finite State Machine) has flipflops and so you have to
add this value "Td=xx" to your flipflops. See also the Td parameter
in the last gate exmple.

Best Regards
Helmut