Hi Your uploaded example appears to be a transformer with a multi-tapped primary that maintains 18v output at the secondary. I've uploaded an example "Multi_Tapped_Transformer_eT.zip" eT

Hi A while back I uploaded "Multi_VCPot_Test_20240813.zip" that demonstrates how to use multiple vcpots. And...yes..each pot has a hidden pin that expects a voltage source to control the rotation perc

Hi I've uploaded CD4051B, CD4052B and CD4053B models. eT

Oh....you were referring to mosfets and use of the mosfet "pick list". Thanks Tony..

On Mon, Nov 25, 2024 at 09:35 AM, Tony Casey wrote: On 25/11/2024 18:04, Andy I via groups.io wrote: Each .SUBCKT would have one .MODEL line. I recommend copying LTspice's NMOS.asy or NMOS4.asy symbol

Hi I'd prefer a separate section in the status bar, at the right end, specifically to display this. For example: | other simulation information... | Solver: norm | Method: trap | Or something like tha

Yes….just an FYI…

This is an excerpt from: Units & Symbols for Electrical & Electronic Engineering © The IET 2016, Chapter 14, page 28 14. Letter and Digit Code for R & C Values For resistors, R, K, M, G and T are used

Uploaded: LM317A Voltage Regulator Ver. 002. includes Model file, Symbol, Test Circuit. Corrects problems with Ver. 001 eT

I've uploaded cdu-demo_eT.zip. This circuit includes the turnout control switches and turnout solenoids (shown as inductors) as described in the article. The inductor values are a guess. The control s

Not on my simulation, it starts in off state.

On Sun, Oct 20, 2024 at 10:25 AM, Bell, Dave wrote: I was modelling an EDN Design Idea posted a few days ago. Works pretty much as designed, except it defaults to the On state when power is applied. S

On Sun, Sep 29, 2024 at 12:17 PM, Bell, Dave wrote: I found this document, which appears to be comprehensive, but a bit daunting, and probably more exacting than I need: https://codeinsecurity.wordpre

Hi photos of curves are very valuable. but there would be added value if you posted the schematics used to generate the curves..

There is mention of the change in the changelog.txt ...... 08/29/24 Updated some bipolar standard devices from standard.bjt 08/29/24 Updated list of jfet devices to currently supported ones ......

On Tue, Sep 3, 2024 at 10:36 AM, Tony Casey wrote: On 03/09/2024 18:11, eetech00 via groups.io wrote: I ran FET VCA.asc on recently installed LTspice 24.0.12 (installed two days ago). The schematic si

Hi, I ran FET VCA.asc on recently installed LTspice 24.0.12 (installed two days ago). The schematic simulated with no problems. standard.jfet still contains PN4391.

1. Click the waveform label, then press F4 or 2. Click the waveform label, Rht-clk on waveform pane, Choose "Note & Annotations", "Cursor Position"

On Tue, Aug 13, 2024 at 11:33 AM, John Woodgate wrote: Must confuse a PCB layout app! No. Not really. The footprint in the PCB part library wouldn’t be assigned a physical pin that matches the logical

Andy, kudos....Your interpretation and description is accurate...