elifdemirci0864 wrote, "I see my fault so I have uploded again simulation result. I am sorry for this mistake .( You can see: Photo albüm -> LTspice simulation results of FinFET and MOSFET circuit-> 4

Is it possible to share this LTSpice model or to let me know where I can find it or similar ones? Thanks, Seth

Bob wrote, "it depends a lot on transistor orientation and other mask effects, and the layout parasitics often dominate the device intrinsic parasitics." Yes, that is the job of the parasitic extracti

elifdemirci0864 wrote: "Files->Temp->20nm-finfet.rar" Fortunately you did not upload it yet. When you get around to uploading it, make sure that it is a .zip file, not a .rar file. Andy

Keshav wrote that there were problems simulating the circuit in https://groups.io/g/LTspice/files/z_yahoo/Files%20sorted%20by%20message%20number/msg_65703/32nm_finfet.rar . It looks to me like that is

Keshav wrote, "I'm also facing the same issue. Can anyone help me too?" Keshav, what exactly is "the same issue"? Why have you not followed the other advice that people gave you already? There were re

There was some discussion here about 13 months ago about "soinmos1.pm" models. Files > z_groups.io > Files sorted by message number > msg_123900 https://groups.io/g/LTspice/files/z_groups.io/Files%20s

Someone named "ayodejidavid18" uploaded a couple of schematics a few hours ago, but forgot to send a message. Did you forget to send it? Please, remember that you must send a message if you have somet

The sims will always tell you that Level=72 is unknown. You can't stop that, except by not using level 72. That is a fact. Some of your options are: Get the models from the actual FAB you will use. I

shivacharya125 asked about modifying models for FINFETs. Usually, we get models from the vendors who make the ICs. Do you have .MODEL statements for the devices you will be using? Does your vendor mak

Hello Andy, Looks like i dont have to work on that project anymore. But I will like to thank you for your help. I really appreciate it. Thank you All the best Regards Karan

amaraambica18 wrote: "... but when we tried to run it we encountered a problem saying "could not open include file /soinmos.pm"." That error message generally means that the file is not where you told

Hello Andy " It has SPICE control lines (.DC and .PRINT an .END statement). Those don't belong in a model file. It has other voltage sources that are not part of the model. " You are OK. That's why I

Hello miteshtopiwala@... Questions should be written in an extra message with a meaningful subject. > I have downloaded FinFet-DG-45nm PTM file and created symbols for PMOS and NMOS using LTspic

Thank u bro I will try all this methods which u specified if in get any doubt I will get back to u thanks once again for helping me From:"Vlad imbvlad@... [LTspice]" Date:Thu, 9 Oct, 2014 at 11:

I agree Helmut. Thanks for the help. Rafay

Hello, You can graph the drain current Id. Vgs=0V -> Ioff Vgs=Vcc -> Ion Best regards, Helmut

Echa, Files in the Temp directory are temporary. Hence the name Temp. After a few days, Helmut moves them to a permanent folder. Open this file: Files > Tables of Contents > all_files.htm and search i

Hello, I have uploaded an example using the parameters width and length. Right-mouse-click on the FET in the schematic and enter the parameters in SpiceLine as shown below. len=45n wid=60n Files > Fil