They can work on the bugs to their hearts content, but it might be reasonable to leave the link there so more people can continue the search.

Anything is possible if you know what you are doing. Why not post your files by uploading them to the \Temp folder. That way we are in a better position to help you. Best method is to combine the into

The link to the beta release appers to be broken. Is this intentional or just an accident?

I understand that, but you must first convince yourself that you have a method which can gather the data you seek. THEN, it will be time to see if LTspice is up to the task. You're putting the cart be

You might also be interested in a book on Inductors by Marcos Alonso. He uses a combination of Python and LTspice to do the modeling. Amazon.com: Inductors: Variable and Controllable: 9798500248169: A

Only if you understand what is going on. Given that most LTspice simulations involve creatin a graphical schematic rather than a text based netlist I'm surprised it came up with an approach that is so

This is really more of a design question than an LTspice question. You might have better chances of a useful answer by going to a forum focused on IC design.

What kind of modulation did you have in mind? There are at least five different methods I can thnk of off the top of my head. There are standard components that will do modulation for you. They are in

It can be shown that no pseudo-random process is truly random in the sense that Beta decay is random and unpredictable.

The drop-down menu and Ctrl-L BOTH refer to the "SPICE Output Log". References to the "SPICE Error Log" appear to be deprecated. There are still 3 hits for "Error Log" in the documentation. Documentat

This feature is often referred to as UVLO or Under Voltage Lockout. It does not necessarily use a Schmitt Trigger; It is more likely just a comparator.

I checked the file XL4016.sub from @Bordodynov and the previous file uploaded by Andy I, named XL4016.cir, and there are a few differences. I have not tried an example circuit with it except to verify

I have also uploaded the symbol and subcircuit from the collection of @Bordodynov

Perhaps the noise source is suffering from RDS (aka Reality Detachment Syndrome).

Perhaps a newly assigned engineer did something untoward to the "pooch".

And you know there is a model for this DCDC regulator on some chip because.... Help us out and tell which of the chips in the vast array of possible semiconductors you could be talking about. IMHO the

The closest match I have is STW12NK90Z and it is the only model that has the handle "STW12N". On that basis I think you're SOL.

The manufacturer is likely to be the best source. Why do you think another source would have the inside track on the model parameters?

Not with LTspice. There are other simulators that support Verilog digital, but not Verilog-A as far as I know.

The normal definition of common mode is ((V+)+(V-)/2) or one-half the sum of the two voltages.