Dear Friends, I am new to LTspice and I have been struggling with figuring out what information my ASCII RAW file contains. I have plotted the frequency response of a filter circuit. In my ASCII RAW file, I want to see the values of the frequencies and the corresponding values of the voltages. Below, I am including the contents of my ASCII RAW file. In this file, I thought that the entries against the left most 0 immediately after "Values:" are the frequencies. But, these values are not in the range 10 Hz to 100 kHz. I don't see anything in the RAW file that resembles frequencies. Maybe I am looking in the wrong place in the file? By the way, I got my ASCII RAW file by checking the "ASCII Date Files" check box in Tools --> Control Panel --> Compression. Thank you very much for any help you can give. - Ram. Title: * C:\EE221\PotluriSpring2003\Project\ABPF.asc Date: Tue Apr 22 22:40:17 2003 Plotname: AC Analysis Flags: complex forward log No. Variables: 93 No. Points: 201 Offset: 0.0000000000000000e+000 Command: Linear Technology Corporation LTspice Backannotation: u1 3 2 7 4 6 Backannotation: u2 3 2 7 4 6 Backannotation: u3 3 2 7 4 6 Backannotation: u6 3 2 7 4 6 Backannotation: u4 3 2 7 4 6 Backannotation: u5 3 2 7 4 6 Variables: 0 frequency frequency 1 V(nc_02) voltage 2 V(n001) voltage 3 V(nc_01) voltage 4 V(out1) voltage 5 V(n002) voltage 6 V(in) voltage 7 V(nc_04) voltage 8 V(n003) voltage 9 V(nc_03) voltage 10 V(out2) voltage 11 V(n004) voltage 12 V(nc_06) voltage 13 V(n005) voltage 14 V(nc_05) voltage 15 V(out3) voltage 16 V(n006) voltage 17 V(out4) voltage 18 V(n008) voltage 19 V(n007) voltage 20 V(out5) voltage 21 V(n010) voltage 22 V(n009) voltage 23 V(nc_08) voltage 24 V(n011) voltage 25 V(nc_07) voltage 26 V(out) voltage 27 V(nc_09) voltage 28 V(nc_10) voltage 29 V(nc_11) voltage 30 V(nc_12) voltage 31 I(C10) device_current 32 I(C9) device_current 33 I(C8) device_current 34 I(C7) device_current 35 I(C6) device_current 36 I(C5) device_current 37 I(C4) device_current 38 I(C3) device_current 39 I(C1) device_current 40 I(C2) device_current 41 I(R22) device_current 42 I(R21) device_current 43 I(R20) device_current 44 I(R19) device_current 45 I(R18) device_current 46 I(R16) device_current 47 I(R15) device_current 48 I(R14) device_current 49 I(R13) device_current 50 I(R12) device_current 51 I(R11) device_current 52 I(R10) device_current 53 I(R9) device_current 54 I(R8) device_current 55 I(R7) device_current 56 I(R6) device_current 57 I(R5) device_current 58 I(R4) device_current 59 I(R3) device_current 60 I(R1) device_current 61 I(R2) device_current 62 I(V1) device_current 63 I(U1:3) subckt_current 64 I(U1:2) subckt_current 65 I(U1:7) subckt_current 66 I(U1:4) subckt_current 67 I(U1:6) subckt_current 68 I(U2:3) subckt_current 69 I(U2:2) subckt_current 70 I(U2:7) subckt_current 71 I(U2:4) subckt_current 72 I(U2:6) subckt_current 73 I(U3:3) subckt_current 74 I(U3:2) subckt_current 75 I(U3:7) subckt_current 76 I(U3:4) subckt_current 77 I(U3:6) subckt_current 78 I(U4:3) subckt_current 79 I(U4:2) subckt_current 80 I(U4:7) subckt_current 81 I(U4:4) subckt_current 82 I(U4:6) subckt_current 83 I(U5:3) subckt_current 84 I(U5:2) subckt_current 85 I(U5:7) subckt_current 86 I(U5:4) subckt_current 87 I(U5:6) subckt_current 88 I(U6:3) subckt_current 89 I(U6:2) subckt_current 90 I(U6:7) subckt_current 91 I(U6:4) subckt_current 92 I(U6:6) subckt_current Values: 0 1.000000000000000e+001,0.000000000000000e+000 -6.994589353925713e-002,-6.224300513311931e-001 -1.039942959774823e-004,1.256131856356748e-005 -6.994595019897262e-002,-6.224305540919555e-001 -7.028059198394734e-002,-6.177420007959171e-001 5.041099463820574e-001,-5.726535027250970e-002 1.000000000000000e+000,0.000000000000000e+000 -2.864690391666699e-003,-8.919041648280660e-002 -1.489921218869175e-005,6.036529832831230e-007 -2.864692196012326e-003,-8.919047190403354e-002 -2.867276849004460e-003,-8.912817436223740e-002 5.912946460149122e-001,-1.891218990771428e-002 -1.915953483657730e-005,-2.765623930620602e-003 -4.621261803662982e-007,7.080401343141798e-009 -1.91

I am trying to use the TABLE form to define an Arbitrary Current Source (B). I have done it in other Spices but just can't seem to get the syntax right in LTSpice. Does anyone have the correct syntax or an example for using TABLE with an arbitrary source in LTSpice?

Thanks for the help on the Table format. It is nice to get this kind of help and support.

The "Edit Simulation Command" dialog box says: "Maximun Timestep:" where it should say: "Maximum Timestep:" Jon

Hello Steve, thanks for this fine example of using the rand-function. Arnold * *

I've been just a little pensive about LT Spice accuracy. So today I sat down with some paper and a relatively simple problem and worked through some derivations to test LT Spice. Assume the following circuit (I'm including a short LT Spice .ASC file at the end of this post, if desired.): ,-- V | | / \ R1 / | R2 | [Vnode] PWM >---/\/\/---x | | C1 ----- ----- | | gnd The PWM input is a square wave with given period, duty time, and voltage. The voltage of this PWM swings from 0V to some other, specified voltage (not necessarily the same as V on the diagram.) Given sufficient time, the voltage at Vnode should establish itself as some stable point, where the rise and fall in voltage are equal to each other. If you were to look at Vnode with an oscilliscope (with the right component values, of course), you should see a small-swing sawtooth, roughly, resting on a stable bias voltage. I was interested in solving that and seeing if LT Spice would hit it, dead on. ---------------- MATH DEVELOPMENT ---------------- Skip this, if you want to just get to the point. But I wanted to develop the mathematics here, in case there was any question about it. First off, modeling this breaks down into two states for the circuit: ,-- V ,-- V | | | | / / \ R1 \ R1 / / | | R2 | [Vnode] | [Vnode] Vp >---/\/\/---x ,----x | | | | C1 | | C1 ----- / ----- ----- R2 \ ----- | / | | | | gnd gnd gnd CASE 1 CASE 2 In case 1, the Thevenin voltage and resistance is: Va = (V * R2 + Vp * R1) / (R1 + R2) Ra = R1 * R2 / (R1 + R2) In case 2, the Thevenin voltage and resistance is: Vb = V * R2 / (R1 + R2) Rb = R1 * R2 / (R1 + R2) Note that Ra is always equal to Rb, so let's just call them R, instead. R = Ra = Rb and for convenience, C = C1 Both cases are analyzed similarly. There is a voltage at Vnode at the start of the time period, which decays away, and the Thevenin voltage towards which the node rises, also on an exponential. Intuitively, this is the sum of two exponentials, but the derivation is worth doing, as a verification of intuition. I(C) = -I(R) = (V - Vnode) / R = C * dVnode / dt Solving this, yields: Vnode = V * (1 + k * e^(-t/RC)) where k is a constant of integration. We know that at t=0, that Vnode is equal to the initial capacitor voltage, which I'll call Vstart. Knowing this, we can solve for k, as: k = (Vstart / V) - 1 Putting k back in, gives: Vnode = V * (1 - e^(-t/RC)) + Vstart * e^(-t/RC) This is exactly as expected. The sum of two exponentials, one describing the disappearing Vstart and the other describing the rise towards the new V. Eventually, all memory of Vstart is lost and V is fully memorized, so to speak. Okay, this gives us a tiny picture of the change for some small value of t, and for either case 1 or case 2. However, I need to put all this together in order to find out when the sum of those two exponentials in case 1 balances with the sum of those two in case 2. That's when the voltage goes up exactly the same amount as it later goes down (or the reverse view, if you like.) Anyway, here's how I approached that. Let's look at the two time periods of the square wave: _____ _____ .... Vp | | | | _____| |__________| |_________.... 0 ^ ^ ^ : : : : ton : toff : We'll also set: tcyc = ton + toff During toff, the voltage at Vnode follows this: Vend = Vb*(1 - e^(-toff/(R*C)) + Vstart1*e^(-toff/(R*C)) But to get Vstart1, we need to examine what happens during ton, so: Vstart1 = Va*(1 - e^(-ton/(R*C)) + Vstart*e^(-ton/(R*C)) Now, in the static case: Vend = Vstart So solving the above pair of equations with that equality for Vstart, yields: Vb - Va*e^(-tcyc/(R*C)) + (Va-Vb)*e^(-toff/(R*C)) Vstart = ------------------------------------------------- 1 - e^(-tcyc/(R*C)) I just call Vstart here, VnodeLO. That differentiates the term from VnodeHI, which is the peak reached at the end of ton. So here are the two equations which describe these two voltages: Vb - Va*e^(-tcyc/(R*C)) + (Va-Vb)*e^(-toff/(R*C)) VnodeLO = ------------------------------------------------- 1 - e^(-tcyc/(R*C)) and Va - Vb*e^(-tcyc/(R*C)) + (

I just wanted to pass along a little tip when using DFLOP special function models. The rise and fall times default to 0 which will cause incorrect switching when the flops are cascaded. You have to add a Trise=xx value to the flop's Spiceline. According to the help, Tfall will default to specified Trise so does not need to be explicitly specified. Hopefully this might help save a bit of head-sratching. Mike

If I were placing a MOSFET e.g. W=5u L=0.5u , and the length of the source and drain implants might be LS=1u LD=1u. LS,LD could be defined with a .PARAM spice directive. In some netlisters, the parameters AD AD PD PS NRS NRD can be calculated automatically, e.g. AD=W*LD PD=2*LD+2*W NRS=LD/W. Can the LTSpice netlister do this? I can set .PARAM LD=1u, and I can use it in the "Monolithic MOSFET" popup attribute menu, but I can't pick up the device W for the equation {W*LD} to enter in the AD box. Regards, Norbert

Dear Mike and Helmut (and others): I've been trying to use microwave and other devices which are only expressed in s2p format, for which the company does not offer a SPICE model. I followed the Pspice application note in converting s2p data into a 2-port spice model. I believe my resulting figures are correct. However, LTspice 2.02p (Apr 24 2003) crashes with the following message: SCAD3 caused an invalid page fault in module SCAD3.EXE at 0177:005465ce. Registers: EAX=009c4be0 CS=0177 EIP=005465ce EFLGS=00010202 EBX=0099d840 SS=017f ESP=00c7f868 EBP=00c7fa94 ECX=00000001 DS=017f ESI=00a99350 FS=218f EDX=00000424 ES=017f EDI=009c4be0 GS=0000 Bytes at CS:EIP: 83 39 01 7e 0d 68 74 e5 68 00 e8 13 c9 fa ff 83 Stack dump: 00a99354 00000001 00a99350 000027e4 0000001c 0000002c 00000020 009c4be0 00000000 0096000c 00960000 00995708 00000000 00000001 00611660 00000000 Can you or anyone else please tell me if I need to configure something differently, or is this actually a bug which needs to be fixed, and if so, when can us we expect an update? I'm placing the data in this post in case you have attachment blockers. Thanks in advance!!! Andrew McClelland eternalsquire@... My data is as follows: ------------- coilcraft.net ------------- * C:\WINDOWS\Desktop\designs\coilcraft.asc V1 N002 0 SINE(0 1 60000) R2 N001 0 1000000 X1 N002 N001 N003 06cs3n3 R1 N003 0 1000000 .tran 0 .0001 0 .00001 .inc d:\progra~1\ltc\swcadiii\lib\sub\06cs3n3.sub .backanno .end ------------- coilcraft.asy (located in d:\progra~1\ltc\swcadiii\lib\sym) ------------- Version 4 SymbolType CELL RECTANGLE Normal 32 13 -34 -15 TEXT 1 51 Bottom 0 CoilCraft SYMATTR Prefix X SYMATTR SpiceModel 06cs3n3 SYMATTR Description CoilCraft Inductor PIN -32 0 LEFT 8 PINATTR SpiceOrder 1 PIN 32 0 RIGHT 8 PINATTR SpiceOrder 2 PIN 0 16 BOTTOM 8 PINATTR SpiceOrder 3 ----------- 06cs3n3.s2p ----------- ! Coilcraft 0603CS-3N3 Chip Inductor ! 1 August 2002 # MHZ S MA R 50 !Freq MagS11 AngS11 MagS21 AngS21 MagS12 AngS12 MagS22 AngS22 1 0.000234224326 62.2575033 0.99989099 -0.0118787051 0.99989099 -0.0118787051 0.000234224326 62.2575033 43.64 0.00906313175 85.638131 0.999351559 -0.518118178 0.999351559 -0.518118178 0.00906313175 85.638131 86.28 0.0178923066 86.2661558 0.998994383 -1.02406187 0.998994383 -1.02406187 0.0178923066 86.2661558 128.92 0.0267155736 86.2623404 0.998614361 -1.52973496 0.998614361 -1.52973496 0.0267155736 86.2623404 171.56 0.0355316588 86.0555185 0.998185387 -2.03511166 0.998185387 -2.03511166 0.0355316588 86.0555185 214.2 0.0443391802 85.7538407 0.997697385 -2.54015386 0.997697385 -2.54015386 0.0443391802 85.7538407 256.84 0.053136687 85.3990479 0.997145294 -3.04481802 0.997145294 -3.04481802 0.053136687 85.3990479 299.48 0.0619226905 85.0111173 0.996526228 -3.54905776 0.996526228 -3.54905776 0.0619226905 85.0111173 342.12 0.0706956814 84.6009777 0.99583843 -4.05282503 0.99583843 -4.05282503 0.0706956814 84.6009777 384.76 0.0794541408 84.1751868 0.995080807 -4.55607082 0.995080807 -4.55607082 0.0794541408 84.1751868 427.4 0.0881965474 83.7379567 0.994252689 -5.05874552 0.994252689 -5.05874552 0.0881965474 83.7379567 470.04 0.0969213827 83.2921396 0.993353696 -5.56079926 0.993353696 -5.56079926 0.0969213827 83.2921396 512.68 0.105627135 82.8397501 0.992383657 -6.06218202 0.992383657 -6.06218202 0.105627135 82.8397501 555.32 0.114312302 82.3822618 0.991342565 -6.56284388 0.991342565 -6.56284388 0.114312302 82.3822618 597.96 0.122975394 81.9207845 0.990230534 -7.06273504 0.990230534 -7.06273504 0.122975394 81.9207845 640.6 0.131614937 81.4561755 0.989047786 -7.56180599 0.989047786 -7.56180599 0.131614937 81.4561755 683.24 0.140229472 80.9891118 0.987794624 -8.06000753 0.987794624 -8.06000753 0.140229472 80.9891118 725.88 0.14881756 80.5201383 0.98647143 -8.55729087 0.98647143 -8.55729087 0.14881756 80.5201383 768.52 0.157377781 80.0497013 0.985078648 -9.05360771 0.985078648 -9.05360771 0.157377781 80.0497013 811.16 0.165908737 79.5781722 0.983616781 -9.54891023 0.983616781 -9.54891023 0.165908737 79.5781722 8

Hello, I have a problem with new symbol designing! I'd like to design a simple amplifier circuit with the OpAmp TL071. For that, I drawed a new symbol: TL071.asy I set the attribute "Prefix : X" I also set the attribute "SpiceModel" to the filename TL071.lib, which can be found in the directory C:\Programme\LTSpice\lib\sub\. In the file TL071.lib, I saved the subcircuit like this: .SUBCKT TL071 1 2 3 4 5 C1 11 12 3.498E-12 C2 6 7 15.00E-12 DC 5 53 DX and so on... Unfortunately, I don't get no circuit with the so-defined TL071 to work. The error message tells: "Error: Unknown device type in: xu1 n004 n001 n002 0 n002 tl071" I think, it is because I didn't clearly define the library file where the TL071 subcircuit is saved. But I don't know no way to define a library in a schematics file. What could I do to get my circuit with my self-designed OpAmp-Model to work? Sincerely Yours, Bernhard ______________________________________________________________________________ UNICEF bittet um Spenden für die Kinder im Irak! Hier online an UNICEF spenden: https://spenden.web.de/unicef/special/?mc=021101

What are some good magazines or journals to watch for info on circuit simulation, modeling, and SPICE? I can't find any publication that seems to concentrate on these topics. For example, the IEEE Journal of Solid State Circuits published Boyle's paper on opamp macromodeling, but hasn't had a lot of info on the topic in recent years. What should I be reading to keep up? Thanks for your suggestions Dale

I ran a sim with start time=0 and zoomed in on a portion of the waveforms near the end of the sim. I then re-ran the sim with Tstart and Tstop specified as the beginning and end, respectively, of the zoomed waveforms view. For example, let's say I zoomed in so that my time scale started at 895 usec and ended at 927 usec. I then set Tstart=895u and Tstop=927u. To my surprise (and dismay), the results were different! Has anyone else noticed this problem? Thanks, Ron Harrison

There's some new circuit topology checking in version 2.02w to help diagnose these types of problems. Floating nodes are now listed as warnings in the .log file. Note not all floating nodes listed are fatal LTspice errors. For example, if you don't give a DC path to the gate of a JFET, it will be listed as a floating node, even though LTspice has no trouble computing the voltage on the gate since it's not perfectly floating. The new error checking will also detect a loop of voltage sources and/or inductors when there's no Rser in the loop. --Mike --- Bill Lewis <wrljet@...> wrote: __________________________________ Do you Yahoo!? The New Yahoo! Search - Faster. Easier. Bingo. http://search.yahoo.com

Does anybody have suggestions of how to use LTSpice in a 'batch' way, either from Windows or from Linux? I want to write a program loop to build an input netlist file, submit it to LTSpice as a batch job, and pick out results from the raw file. Thanks in advance for any reply.

Some Spices print out a table of device operating point information (e.g. device gm , gds, capacitances) for things like mosfets and bipolar devices. Is this available in LTSpice? Regards, Norbert.

Nachricht Hello * I'm searching for the Spice models for: BJT 2SA1302A Toshiba 2SC3281A Toshiba 2SA1943 Toshiba 2SC5200 Toshiba 2SA1837 Toshiba 2SC4793 Toshiba 2SA1376 NEC 2SC3478 NEC MJL3281A ON MJL1302A ON MJL21193 ON MJL21194 ON FET K3497 Toshiba J618 Toshiba I did not find the Spice models on the web sites so far. --> Does anyone have this data or knows where it's worth to search for it? Thanks a lot ! Mathias

I just happened upon a Greek site which had what appears to be a complete set of PSPICE .LIB files for a 1998 version of ORCAD. These appear to be in a compatible format for LT Spice. For example: .model Q2N2222 NPN(Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 + Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 + Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p + Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6 Vtf=1.7 Xtf=3 + Rb=10) * National pid=19 case=TO18 * 88-09-07 bam creation Are there any caveats for me to consider in simply importing the bipolar and jbipolar libs, lock-stock-and-barrel, into standard.bjt, for example? (Other than the fact that LT Spice updates may replace some on the next update, if the names match up.) There are several thousand BJT models, alone. So, for example, what will happen to LT Spice's BJT model list when I try and designate an NPN or PNP on a schematic? Will the sheer number (approx 1000 each) of these overwhelm memory in the dialog box? Jon

Hi, How do you use the eye diagram function in swcad?

Mike, Would it be possible to add the capability to do an efficiency analysis on a circuit that doesn't use an LT switching regulator IC? I've found this function to be very useful, but not all designs have a switching regulator controller in them. It seems that all that is needed is the ability to set a start and end time for the analysis. This capability would also be helpful for circuits that use an LT controller. Often the efficiency analysis requires the circuit to settle for much longer than is really necessary. This isn't a problem if the simulation takes less than a minute or so, but it's a problem when it takes a half hour or more. Also, it would be useful to be able to get power dissipation info during transient conditions since many of the small parts I use heat up quite quickly. Thanks, John

The measured current in B sources appears to have reversed polarity. When probing on B sources, current flowing from (-) to (+) is reported as positive. This is assuming the first node in the netlist is the (+) terminal. All other devices seem to report current flowing from (+) to (-) as positive. Brad (Example circuit attached) Version 4 SHEET 1 880 680 WIRE -160 240 -160 192 WIRE -160 192 -112 192 WIRE 0 192 0 240 WIRE 160 240 160 192 WIRE 160 192 288 192 WIRE 288 192 288 240 WIRE -32 192 0 192 FLAG 0 320 0 FLAG -160 320 0 FLAG 160 320 0 FLAG 288 320 0 SYMBOL voltage -160 224 R0 WINDOW 123 24 132 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value "" SYMATTR Value2 AC 1 SYMBOL voltage 160 224 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 0 SYMBOL bi 288 240 R0 SYMATTR InstName B1 SYMATTR Value I=i(L1) SYMBOL ind -16 224 R0 SYMATTR InstName L1 SYMATTR Value 1µ SYMBOL res -16 176 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 1m TEXT 120 456 Left 0 !.ac oct 25 1 1meg TEXT -168 120 Left 0 ;however, current probing B1 gives "wrong" polarity compared to L1 TEXT -168 88 Left 0 ;V1 and V2 have identical currents (as expected)